Broadcom
DFT Lead Engineer
$144K–$230K
USA-CA San Jose Innovation Drive · Full-time · Posted Aug 11, 2026
- Experience
- 12+ years with a bachelor’s degree, or 10+ years with a master’s degree, in a relevant engineering field.
- Education
- Bachelor’s or master’s degree in Electrical/Electronic/Computer Engineering.
About the job
Leads ASIC design-for-test programs from specification through implementation, verification, silicon debug, and production release.
What you'll do
- Define DFT specifications and implement DFT features, including scan, MBIST, TAP, LBIST, IO, and SerDes.
- Generate, verify, and debug test vectors; support test timing closure, silicon failure analysis, and yield improvement.
- Automate DFT and test-vector flows and coordinate with customers and engineering and manufacturing teams.
What they ask for
- Strong DFT background, including scan/ATPG, BIST, or IO and analog DFT.
- Experience with scan insertion and compression, ATPG vector generation and debugging, Verilog, and memory BIST.
- Knowledge of boundary scan standards IEEE1149.1 and IEEE1149.6, and IEE1687, IJTAG, ICL, and PDL.
- Ability to code using TCL, PERL, RUBY, PYTHON, C++ or similar.
Nice to have
- ATE experience.
- Experience with Serdes, DDR, PCIE, ENET, or CXL IOBIST verification and silicon debug; Tessent SSN experience is highly desired.
Pay
USD 143,800.00 To USD 230,000.00 (base salary)
Tools
TCL, PERL, RUBY, PYTHON, C++, Verilog, DFT Compiler, Mentor TestKompress
Model-written summary · the original posting is authoritative