Broadcom
Digital Design RTL Engineer
$122K–$195K
USA-Colorado-Fort Collins-4380 Ziegler Road +1 · Full-time · Posted Jul 22, 2026
- Location
- USA-Colorado-Fort Collins-4380 Ziegler Road
USA-CA San Jose Innovation Drive - Experience
- 8+ years of industry experience is highly preferred.
- Education
- BSEE required; MSEE/PHD preferred.
About the job
Designs and delivers SystemVerilog RTL from specification through timing closure and physical-design hand-off, optimizing PPA and addressing crossing and low-power concerns.
What you'll do
- Take designs from initial specification through timing closure and physical-design hand-off.
- Collaborate with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones.
- Deliver high-quality RTL and apply PPA optimization, CDC analysis, and low-power design techniques.
What they ask for
- High proficiency in SystemVerilog.
- Demonstrated delivery of high-quality SystemVerilog RTL in advanced process nodes (5nm and below).
- Deep understanding of RTL design, PPA optimization, CDC analysis, and low-power design techniques.
- BSEE required.
Nice to have
- MSEE/PHD.
- 8+ years of industry experience focused on SoC integration, LPDDR5/6, DDR4/5, high-speed SerDes, or HBM protocols.
Pay
USD 121,900.00 to USD 195,000.00 (base salary)
Tools
SystemVerilog, LPDDR5/6, DDR4/5, SerDes, HBM
Model-written summary · the original posting is authoritative