Broadcom
Digital Design Verification Engineer
$101K–$162K
USA-CA San Jose Innovation Drive +1 · Full-time · Posted Sep 14, 2026
- Location
- USA-CA San Jose Innovation Drive
USA-CA Irvine Alton Parkway Bldg 1 - Experience
- 5+ years of industry experience.
- Education
- BSEE required; MSEE/PhD preferred.
About the job
The engineer sets up UVM testbenches and supports SoC design work from specification through timing closure and physical design hand-off.
What you'll do
- Work autonomously on designs from initial specification through timing closure and physical design hand-off.
- Collaborate with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones.
- Set up UVM testbenches and perform design debug.
What they ask for
- BSEE.
- 5+ years of industry experience focused on SoC integration, UVM testbench setup, and design debug.
- High proficiency in UVM.
Nice to have
- MSEE or PhD.
Pay
USD 101,000.00 To USD 162,000.00 annual base salary
Tools
UVM
Model-written summary · the original posting is authoritative