Broadcom
IC Design Engineer (STA/ Synthesis)
$144K–$230K
USA-CA San Jose Innovation Drive +4 · Full-time · Posted Oct 30, 2026
- Location
- USA-CA San Jose Innovation Drive
USA-CA Irvine Alton Parkway Bldg 2
USA-Allentown-1110 American Parkway NE
USA-Colorado-Fort Collins-4380 Ziegler Road
USA-CO Broomfield - Experience
- 12+ years with a bachelor's degree, 10+ years with a master's degree, or 7+ years with a PhD.
- Education
- At minimum, a bachelor's degree; master's or PhD also accepted.
About the job
Leads timing analysis and synthesis work to develop and validate constraints, perform audits, and close timing for complex IP and ASIC blocks.
What you'll do
- Develop and validate timing constraints; perform STA, synthesis, and static audits.
- Define signoff methodologies, conduct pre-route timing and QoR analysis, and generate timing ECOs to drive closure.
- Automate timing analysis and guide clock tree synthesis and optimization.
What they ask for
- Experience with high-complexity silicon in advanced technology nodes and timing constraint development for hierarchical designs.
- Knowledge of SoC clock tree planning and implementation, timing ECO creation, and final timing signoff.
- Proficiency with STA, synthesis, and audit tools, plus Tcl or Perl scripting.
- Strong understanding of ASIC design flows, including RTL and place-and-route.
Nice to have
- Direct or indirect RTL/design experience.
- Post-graduate coursework.
Pay
USD 143,800.00 To USD 230,000.00 annual base salary
Tools
PrimeTime, TCM, Tempus, Tcl, Perl, DC-T, Genus, Formality
Model-written summary · the original posting is authoritative