Broadcom
Lead ASIC Design Engineer
$144K–$230K
USA-California-San Jose-1320 Ridder Park Drive · Full-time · Posted Jun 19, 2026
- Experience
- 12+ years of direct industry experience in ASIC/SoC digital design.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Visa sponsorship
- Must have legal authorization to work in the US.
About the job
Lead top-level digital architecture and full-chip integration for ASIC/SoC projects, coordinating teams through tape-out and silicon bring-up.
What you'll do
- Own chip architecture, partitioning, integration, timing constraints, and tape-out sign-off.
- Design and optimize synthesizable RTL; drive synthesis, static timing analysis, and static quality checks.
- Coordinate across design, physical design, verification, validation, and software teams; mentor engineers.
What they ask for
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
- Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture; deep experience with front-end EDA tools for synthesis, STA, and CDC analysis.
- Proven history of successful, first-pass silicon tape-outs on modern process technologies; legal authorization to work in the US.
Nice to have
- Experience with mixed-signal or high-speed PHY-adjacent architectures such as SerDes, PCIe, DDR, or custom interconnects; familiarity with DFT planning.
- Proficiency in Python, Tcl, or Perl scripting.
Pay
$143,800 - $230,000 USD annual base salary
Tools
SystemVerilog/Verilog, SDC, Design Compiler, Genus, PrimeTime, Tempus, SpyGlass, JasperGold CDC
Model-written summary · the original posting is authoritative