Broadcom
Memory System Designer and Place and Route Engineer
$110K–$176K
USA-TX-Austin - River Place B7 · Full-time · Posted Oct 6, 2026
- Experience
- Typically requires a minimum of 8 years of relevant experience.
- Education
- Bachelor in Electrical Engineering.
About the job
Designs and implements memory subsystems, including RTL development, physical design, synthesis, and design closure.
What you'll do
- Architect and design memory subsystems, and implement subsystem RTL.
- Perform place and route, synthesis, and design closure for timing, DRC, LVS, and EM/IR.
- Run and debug logical equivalency checks and develop automation scripts.
What they ask for
- Ability to write and debug Verilog RTL code.
- Place-and-route expertise and proficiency with STA, DRC, and EM/IR tools.
- Ability to code in Python and understanding of synthesis tools and synthesis runs.
- Familiarity with memory behavior.
Pay
USD 109,700.00 to USD 175,500.00 (base salary)
Tools
Verilog RTL, Python, STA, DRC, LVS, EM/IR
Model-written summary · the original posting is authoritative