Package Design Engineer

What you'll do

• Own ASIC package designs and design critical structures for SerDes, ADC/DAC, DDR, and related technologies.
• Manage work across multiple projects, including scheduling, prioritization, tracking, and customer and vendor interfaces.
• Improve design-team efficiency through process development, automation, and documentation.

What they ask for

• BSEE or similar field and 2+ years’ experience in flip-chip-BGA package design, including high-speed SerDes, or an MSEE or PhD.
• Knowledge of electrical engineering fundamentals.
• Self-management and organization skills.
• Cooperate with worldwide teams across multiple time zones, including co-design with internal team members and external vendor designers.

Nice to have

• Working knowledge of package-level signal integrity and power integrity.
• Cadence APD (allegro package designer) or equivalent layout tool; 1 or more years experience with Cadence SKILL for Allegro or similar design-automation coding experience and interest.

Pay

USD 82,500.00 To USD 132,000.00 annual base salary

Tools

flip-chip-BGA, SerDes, ADC/DAC, DDR, Cadence APD (allegro package designer), Cadence SKILL for Allegro

AI focus

Develops high-performance ASIC package designs for artificial intelligence (AI) applications.