Broadcom
Package Design Engineer
$101K–$162K
USA-CA San Jose Innovation Drive +2 · Full-time · Posted Oct 1, 2026
- Location
- USA-CA San Jose Innovation Drive
USA-TX-Austin - River Place B7
USA-Colorado-Fort Collins-4380 Ziegler Road - Experience
- 5+ years with a BSEE or similar field, or 3+ years with an MSEE or similar field.
- Education
- BSEE or similar field, or MSEE or similar field.
About the job
Design high-performance flip-chip-BGA packages for ASICs, including physical layout and signal/power integrity, while coordinating project work and design improvements.
What you'll do
- Own ASIC package designs, covering signal integrity, power integrity, manufacturability, reliability, and thermal considerations.
- Design critical package structures for SerDes, ADC/DAC, and DDR; manage work across multiple projects and coordinate with customers and design partners.
- Improve design-team efficiency through process development, automation, and documentation.
What they ask for
- BSEE or similar field and 5+ years’ experience in flip-chip-BGA package design, including high-speed SerDes; or MSEE or similar field and 3+ years’ work experience.
- Knowledge of package-level signal integrity and power integrity.
- Self-management and organization skills.
- Cooperate with worldwide teams across multiple time zones, including co-design with internal team members and external (Vendor) designers.
Nice to have
- Cadence APD (allegro package designer) experience; equivalent tool is OK.
- 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest.
Pay
USD 101,000.00 To USD 162,000.00 (base salary)
Tools
Cadence APD (allegro package designer), Cadence SKILL, SerDes, ADC/DAC, DDR
AI focus
Design packages for ASICs for artificial intelligence (AI) applications.
Model-written summary · the original posting is authoritative