Broadcom
Physical Design Engineer
$82K–$132K
USA-CA San Jose Innovation Drive · Full-time · Posted Oct 30, 2026
- Experience
- 2 years with a Bachelor's degree; alternatively, a Master’s degree with graduation within the past 12 months.
- Education
- Bachelor's degree in Electrical Engineering or Computer Engineering, or Master’s degree in either field.
- Visa sponsorship
- Legal authorization to work in the U.S. is required
About the job
Executes block-level physical design for custom ASICs, including implementation, timing closure, physical verification, and signoff.
What you'll do
- Run block-level floorplanning and placement-and-route flows using EDA tools.
- Perform static timing analysis, debug timing paths, and execute ECOs; resolve physical verification violations.
- Analyze IR drop and electromigration, and develop automation scripts to improve flow efficiency.
What they ask for
- Bachelor’s degree in Electrical Engineering or Computer Engineering plus 2 years of experience, or a Master’s degree in either field with graduation within the past 12 months.
- Understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
- Familiarity with STA concepts, clocking, and setup/hold timing; hands-on coursework, lab experience, or projects using EDA design tools.
- Proficiency in TCL, Python, Ruby, or Bash.
Nice to have
- Internship or research experience in ASIC physical design, synthesis, or physical verification.
- Basic understanding of DFT, UPF/CPF, and FinFET technologies.
Pay
USD 82,500.00 To USD 132,000.00 annual base salary
Tools
Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, Siemens tools, TCL, Python, Ruby, Bash, UPF/CPF
AI focus
The role supports physical design for AI/ML accelerators and custom cloud ASICs; the team develops AI-driven automation and methodology.
Model-written summary · the original posting is authoritative