Broadcom
Physical Design Engineer
$82K–$132K
USA-CA San Jose Innovation Drive · Full-time · Posted Oct 30, 2026
- Experience
- 2 years with a bachelor’s degree; alternatively, a master’s degree with graduation within the past 12 months.
- Education
- Bachelor’s degree in Electrical Engineering or Computer Engineering, or a master’s degree in either field.
- Visa sponsorship
- Legal authorization to work in the U.S. is required.
About the job
Executes block-level physical design and signoff tasks for high-performance ASICs, including floorplanning, implementation, timing closure, and verification.
What you'll do
- Run block-level floorplanning and placement-and-route flows; perform static timing analysis and timing-closure ECOs.
- Run physical verification checks and resolve signoff violations; analyze IR drop and electromigration.
- Develop and maintain scripts to improve flow efficiency and productivity.
What they ask for
- Bachelor’s degree in Electrical Engineering or Computer Engineering plus 2 years of experience, or a Master’s degree in either field with graduation within the past 12 months.
- Understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
- Familiarity with static timing analysis, clocking, and setup/hold timing; hands-on coursework, lab, or project experience with EDA design tools.
- Proficiency in TCL, Python, Ruby, or Bash; legal authorization to work in the U.S.
Nice to have
- Internship or research experience in ASIC physical design, synthesis, or physical verification.
- Basic understanding of DFT, UPF/CPF, and FinFET technologies.
Pay
USD 82,500.00 To USD 132,000.00 annual base salary
Tools
EDA, Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, Siemens tools, TCL, Python, Ruby, Bash
AI focus
Physical design work for AI/ML accelerators and custom cloud ASICs; the team also develops in-house AI-driven automation and methodology.
Model-written summary · the original posting is authoritative