Broadcom
Physical Design Engineer
$144K–$230K
USA-CA San Jose Innovation Drive +3 · Full-time · Posted Oct 30, 2026
- Location
- USA-CA San Jose Innovation Drive
USA-Allentown-1110 American Parkway NE
USA-Colorado-Fort Collins-4380 Ziegler Road
USA-CO Broomfield - Experience
- 12+ years with a BS, or 10+ years with an MS, in a related field.
- Education
- BS or MS in Electrical Engineering, Computer Engineering, or a related field.
About the job
Implements ASIC/SoC physical design, including place and route, timing closure, verification, and power optimization, to meet PPA targets and tapeout criteria.
What you'll do
- Perform floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification.
- Run equivalence checks and STA; optimize power and implement timing and functional ECOs.
- Drive tools and methodologies to achieve PPA metrics and meet design milestones.
What they ask for
- Hands-on experience with timing analysis and place-and-route tools for ASIC/SoC design.
- Proficiency in design implementation at block and SoC level.
- BS in Electrical Engineering, Computer Engineering, or related field and 12+ years of related experience; or an MS in those fields and 10+ years of related experience.
- Problem-solving, independent work, adaptability, and communication skills.
Nice to have
- Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, and PrimeTime.
- Full-chip tapeout experience based on 7nm and lower technologies.
Pay
USD 143,800.00 To USD 230,000.00 (base salary)
Tools
Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime
Model-written summary · the original posting is authoritative