Broadcom
Principal Physical Design Engineer
$144K–$230K
USA-CA San Jose Innovation Drive · Principal · Full-time · Posted Oct 30, 2026
- Experience
- 12+ years of hands-on physical design experience.
- Education
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the job
Leads physical design implementation for advanced-node networking, AI/ML accelerator, and cloud ASICs, from floorplanning through signoff and GDSII stream-out.
What you'll do
- Lead block- and top-level implementation using Cadence Innovus, including floorplanning, placement, clock tree synthesis, routing, and GDSII stream-out.
- Drive timing, signal-integrity, power, and power-grid optimization for signoff across advanced technology nodes.
- Perform MCMM static timing analysis and signoff using relevant EDA tools.
What they ask for
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12+ years of hands-on physical design experience taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
- Direct tapeout experience in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- High proficiency with physical design EDA tools and advanced TCL, Python, and Unix shell scripting.
Nice to have
- Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS).
- Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating).
Pay
USD 143,800.00 To USD 230,000.00 (base salary)
Tools
Cadence Innovus, Synopsys PrimeTime, Cadence Tempus, StarRC, QRC, RedHawk, Siemens Calibre, TCL
AI focus
Implements AI/ML accelerator and custom cloud ASICs; team develops AI Driven automation and methodology.
Model-written summary · the original posting is authoritative