Broadcom
Principal Physical Design Engineer, STA
$144K–$230K
USA-CA San Jose Innovation Drive · Principal · Full-time · Posted Oct 30, 2026
- Experience
- 12+ years of hands-on ASIC STA and timing closure experience.
- Education
- Bachelor’s degree in Electrical/Computer Engineering.
About the job
Own full-chip static timing analysis and closure for high-performance ASICs, while improving sign-off flows with AI/ML automation.
What you'll do
- Own final timing closure across PVT corners and author and maintain SDC constraints for functional and test modes.
- Apply AI/ML automation and data mining to reduce STA runtime, improve infrastructure efficiency, and triage timing violations.
- Drive timing ECOs and collaborate with RTL, Physical Design, and DFT teams to optimize PPA.
What they ask for
- Bachelor’s degree in Electrical/Computer Engineering.
- Expert proficiency in PrimeTime/Tempus and advanced MMMC/OCV management.
- Strong scripting skills in Tcl, Python, Perl, and Shell, with experience using AI plugins and data-mining scripts for runtime reduction and reporting.
- Exceptional problem-solving and communication abilities.
Pay
USD 143,800.00 To USD 230,000.00 (base salary)
Tools
PrimeTime, Tempus, Tcl, Python, Perl, Shell, SDC, MMMC
AI focus
Use AI/ML automation, AI plugins, and data mining in STA flows to reduce runtime, improve infrastructure efficiency, and support ML-based corner reduction and timing analysis.
Model-written summary · the original posting is authoritative