Broadcom
Principal Physical Verification Engineer
$144K–$230K
USA-CA San Jose Innovation Drive · Principal · Full-time · Posted Oct 23, 2026
- Experience
- 12+ years of relevant experience.
- Education
- Bachelor’s degree required in Electrical Engineering or Electronics Engineering.
About the job
Performs chip-level physical verification for advanced-node ASICs, resolving integration issues and developing verification methodologies and flows through tape-out.
What you'll do
- Execute chip-level physical verification and resolve issues; set up DRM runsets and advanced-node tool flows.
- Guide top-level floorplan, I/O, and bump-planning rules, and resolve chip-integration and assembly issues.
- Provide technical direction on DRC, LVS, ERC, and PERC methodologies; develop best practices and runtime optimizations.
What they ask for
- Bachelor’s degree in Electrical Engineering or Electronics Engineering.
- Hands-on physical verification experience, including LVS, DRC, ERC, and PERC.
- Foundry rules, DFM, and silicon tape-out/RTO tapeout experience.
- Must work in person at the San Jose site; no remote work allowed.
Nice to have
- Experience with ICV, Calibre, or Pegasus EDA tools, including rule-deck coding.
- Experience resolving advanced-node chip-level DRC/LVS/EMIR issues; Python, Tcl, or Perl scripting.
Pay
USD 143,800.00 To USD 230,000.00 (base salary)
Tools
ICV, Calibre, Pegasus, Python, Tcl, Perl, DRC, LVS
AI focus
The position supports next-generation AI and machine-learning ecosystems through PCIe Switch Products; no specific AI development work is stated.
Model-written summary · the original posting is authoritative