Broadcom
R&D Engineer IC Design 4
$122K–$195K
USA-CA San Jose Innovation Drive +1 · Full-time · Posted Jul 2, 2026
- Location
- USA-CA San Jose Innovation Drive
USA-TX-Austin - River Place B7 - Experience
- Bachelor’s degree and 8+ years of related experience; or master’s degree and 6+ years of related experience.
- Education
- BS/MS in Electrical or Computer Engineering or equivalent.
About the job
Designs and verifies ASIC logic blocks, from architecture and RTL design through synthesis, verification, and timing analysis.
What you'll do
- Define architectures, design logic, develop constraints, and synthesize design blocks.
- Verify designs using simulation and formal verification, and analyze timing from physical implementation.
- Simulate and debug designs with Verilog simulation.
What they ask for
- Experience with complete ASIC or standard-product implementation flow, including RTL synthesis and timing analysis/closure.
- Proficiency with TCL/Perl scripting and synthesis using Synopsys Design Compiler/DC topo or Cadence RTL compiler.
- Timing analysis with Primetime for high-frequency designs and advanced technology nodes/libraries; understanding of liberty LIB models.
- Experience with formal verification tools, Spyglass Lint, RTL and gate-level power analysis, DFT/scan methodology, and version control.
Pay
USD 121,900.00 To USD 195,000.00 annual base salary
Tools
TCL/Perl, Synopsys Design Compiler/ DC topo, Cadence RTL compiler, Primetime, Synopsys Formality, Cadence Conformal, Spyglass Lint, Verilog
Model-written summary · the original posting is authoritative