Broadcom
RTL integration Engineer
$144K–$230K
USA-CA San Jose Innovation Drive · Full-time · Posted Jul 31, 2026
- Experience
- 12+ years of related experience.
- Education
- Bachelor's degree.
About the job
Performs SoC-level IP integration and test/debug-mode verification, including RTL design, analysis, synthesis, simulation, and timing support.
What you'll do
- Integrate IP and verify IP test/debug modes at the SoC level.
- Create RTL designs and perform linting, CDC and RDC analysis, and synthesis.
- Support Palladium modeling and STA, and debug simulation failures.
What they ask for
- Extensive knowledge of implementation, synthesis, and timing issues.
- Strong understanding of UVM and SystemVerilog.
- Deep familiarity with zero-delay and SDF simulations, including debugging failures.
- Proven gate-level simulation (GLS) experience and familiarity with CDC analysis for RTL and gate-level designs.
Nice to have
- Experience with NCSim and VCS.
Pay
USD 143,800.00 to USD 230,000.00 annual base salary
Tools
RTL, UVM, SystemVerilog, SDF, GLS, CDC, NCSim, VCS
Model-written summary · the original posting is authoritative