Broadcom
Senior Physical Design Engineer
$122K–$195K
USA-CA San Jose Innovation Drive · Senior · Full-time · Posted Oct 27, 2026
- Experience
- 8+ years of hands-on physical design experience.
- Education
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the job
Leads physical design implementation of complex AI and PCIe switch ASICs from RTL through tape-out, including timing, power, and signoff.
What you'll do
- Lead block- and top-level implementation from floorplanning through GDSII stream-out.
- Execute placement, clock-tree synthesis, routing, and timing and power optimization on advanced technology nodes.
- Perform MCMM static timing analysis, signal-integrity optimization, and power-grid signoff.
What they ask for
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 8+ years of hands-on physical design experience taping out complex, high-frequency, ultra-large-scale networking or AI ASICs.
- Direct tape-out experience in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- Proficiency with physical design tools and advanced TCL, Python, and Unix shell scripting.
Nice to have
- Strong background in high-speed clock network implementation.
- Experience with power-aware implementation flows, UPF/CPF, multi-voltage domains, and clock/power gating.
Pay
USD 121,900.00 To USD 195,000.00 annual base salary
Tools
Cadence Innovus, Synopsys PrimeTime, Cadence Tempus, StarRC, QRC, RedHawk, Siemens Calibre, TCL, Python, and Unix shell scripting
AI focus
Physical design and tape-out of next-generation AI ASICs.
Model-written summary · the original posting is authoritative