Broadcom
Senior Serdes System Design Engineer/Architect
$144K–$230K
USA-TX-Austin - River Place B7 +2 · Senior · Full-time · Posted Aug 13, 2026
- Location
- USA-TX-Austin - River Place B7
USA-CA San Jose Innovation Drive
USA-CA Irvine Alton Parkway Bldg 1 - Experience
- 12+ years with a B.S.E.E. or 10 years with an M.S.E.E.
- Education
- B.S.E.E. or M.S.E.E.
About the job
Designs, simulates, verifies, and validates signal-processing systems and architectures for high-speed Serdes products, supporting production and next-generation wireline standards.
What you'll do
- Develop channel models, Serdes architectures, system simulations, and signal-processing block requirements.
- Build bit-exact MATLAB and C/C++ models; support RTL vector-matching verification and develop and debug firmware.
- Test and debug Serdes in the lab, document designs, and support standards development and customer engagements.
What they ask for
- B.S.E.E. plus 12+ years of relevant experience, or M.S.E.E. plus 10 years.
- Expert knowledge of Communication Theory and Digital Signal Processing algorithms.
- Working knowledge of analog circuit behavior, transmission line theory, and s-parameters.
- Expertise in MATLAB and C/C++ programming, plus hands-on lab skills.
Nice to have
- Experience designing high-speed CDR PLLs or wireline equalization techniques.
- RTL coding; knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes and PCIe Gen6/Gen7 standards.
Pay
USD 143,800.00 To USD 230,000.00 (base salary)
Tools
MATLAB, C/C++, RTL, IEEE 802.3, OIF 100G/200G/400G Serdes, PCIe Gen6/Gen7
Model-written summary · the original posting is authoritative