Broadcom
Senior Serdes System Design Engineer/Architect
$122K–$195K
USA-TX-Austin - River Place B7 +2 · Senior · Full-time · Posted Sep 1, 2026
- Location
- USA-TX-Austin - River Place B7
USA-CA San Jose Innovation Drive
USA-CA Irvine Alton Parkway Bldg 1 - Experience
- B.S.E.E. plus 8+ years relevant experience OR M.S.E.E. plus 6 years required.
- Education
- B.S.E.E. or M.S.E.E.
About the job
Designs and validates signal-processing architectures and algorithms for high-speed Serdes products, collaborating across design and test teams and supporting standards development and customers.
What you'll do
- Develop channel models, simulations, and Serdes architecture and signal-processing block requirements.
- Build MATLAB and C/C++ system models, verify designs with RTL simulations, and develop/debug physical-layer firmware.
- Test and debug Serdes in the lab; document designs and support standards, marketing, and customers.
What they ask for
- B.S.E.E. plus 8+ years relevant experience OR M.S.E.E. plus 6 years required.
- Expert knowledge in Communication Theory and Digital Signal Processing algorithms.
- Working knowledge of Analog circuit behavior and Transmission line theory and s-parameter.
- Expert in MATLAB, C/C++ programming; good hands-on skills in the lab.
Nice to have
- Experience in designing high-speed Clock and Data Recovery (CDR) PLLs or wireline equalization techniques.
- RTL coding; knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards.
Pay
USD 121,900.00 To USD 195,000.00 annual base salary
Tools
Serdes, PAM, FEC, MATLAB, C/C++, RTL, IEEE 802.3/OIF, PCIe Gen6/Gen7
Model-written summary · the original posting is authoritative