ByteDance
ASIC Design Engineer (Video Silicon IP)- Multimedia Lab
San Jose, California · Full-time · Posted Oct 28, 2026
- Experience
- 2 years of ASIC front-end design experience as a primary RTL owner.
- Education
- M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
About the job
Designs high-performance, low-power ASIC hardware IP for video encoding and processing, from microarchitecture through RTL implementation and validation.
What you'll do
- Develop microarchitectures and RTL for multi-standard video codec pipeline stages, meeting area, power, and performance targets.
- Translate codec specifications and algorithm improvements into implementable hardware architectures with algorithm, architecture, and verification teams.
- Support functional verification, debug coverage, and collaborate on synthesis, timing analysis, CDC/RDC checks, and physical-design closure.
What they ask for
- M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- At least 2 years of ASIC front-end design experience as a primary RTL owner.
- Proficiency in SystemVerilog RTL design or High level Synthesis (HLS); familiarity with UVM/DPI/C++.
- Solid VLSI design knowledge and Python scripting proficiency for EDA flow automation.
Nice to have
- Experience with video codecs, ISP, machine-learning-based image/video compression, or FPGA prototyping.
- Practical experience using LLMs (e.g., GitHub Copilot, Claude, ChatGPT) to assist RTL design workflows.
Tools
SystemVerilog, Verilog, HLS, UVM, DPI, C++, Python, AXI/APB
AI focus
Preferred: Use LLMs to assist RTL design workflows; experience with machine-learning-based image/video compression is also a plus.
Model-written summary · the original posting is authoritative