Drimva

ByteDance

Senior Cloud Acceleration Engineer - DPU & AI Infrastructure (Multiple Positions)

Seattle, Washington · Senior · Full-time · Posted Oct 28, 2026

Experience
2 years of related work experience with a master's degree, or 5 years of post-bachelor’s progressive related work experience with a bachelor's degree; additionally, 2 years in each of the listed experience areas.
Education
Master's or bachelor's degree (or foreign equivalent) in Computer Science, Engineering (any), Information Systems, Data Science, Mathematics, or a related field.

About the job

Designs and optimizes DPU networking software and hardware-accelerated infrastructure for networking, storage, distributed training, and inference.

What you'll do

  • Develop high-performance, low-latency, reliable DPU networking software and co-design solutions with hardware teams.
  • Optimize performance across OS kernels, drivers, and user-space runtime systems; explore acceleration for AI/ML infrastructure.
  • Contribute to architecture and research directions, technical proposals, and mentoring junior team members.

What they ask for

  • At least 2 years of experience with each: writing testable, maintainable, low-latency software in a high-level language; GPU- or ASIC-based computing for machine learning; programming in Linux using C/C++, CUDA, or Python; maintaining and debugging software services; and analyzing error logs and resolving, documenting, and preventing issues.
  • Experience with high-level programming languages including Golang, Java, Python, or C++.
  • Must meet one education/experience path: a master's degree or foreign equivalent in a listed or related field plus 2 years of related experience; or a bachelor's degree or foreign equivalent in a listed or related field plus 5 years of post-bachelor’s progressive related experience.

Pay

USD $207480 - $368220 per year (base salary)

Tools

Golang, Java, Python, C++, Linux, CUDA, GPU, ASIC

AI focus

Explore AI/ML infrastructure acceleration using DPUs, GPUs, and custom hardware to optimize distributed training and inference.

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)