Cerebras
Lead RTL Design Engineer
$200K–$299K
Sunnyvale, CA · On-site · Full-time · Posted Aug 7, 2026
- Experience
- 8-15 years of experience delivering complex, high-performance, high-quality RTL designs.
- Education
- Master’s degree in Computer Science, Electrical Engineering, or equivalent.
About the job
Leads RTL design and integration for future Cerebras Wafer Scale Engine chips, from architecture and development through production and silicon bring-up.
What you'll do
- Drive functional specification, micro-architecture, RTL development, and synthesis; manage the external ASIC vendor through product development.
- Collaborate with physical design, verification, DFT, software, and system teams to meet PPA goals and optimize product functionality and performance.
- Debug functional, timing, and power issues during silicon bring-up.
What they ask for
- Master’s degree in Computer Science, Electrical Engineering, or equivalent.
- 8-15 years of experience delivering complex, high-performance, high-quality RTL designs.
- Front-end chip integration and third-party IP integration experience; demonstrated experience in networking, high-performance computing, machine learning, or related fields; multiple silicon successes.
- Experience managing external vendors and designing or integrating high-speed I/O; networking stack experience including TCP/IP, RDMA, and Ethernet; knowledge of PCIe, CPU interfaces, and Serdes; working knowledge of Python and TCL.
Nice to have
- Experience with FPGA development toolchain, including Place and Route, Floor planning, and Timing Analysis.
Pay
$200,000 to $299,000 annually (base salary)
Tools
RTL, TCP/IP, RDMA, Ethernet, PCIe, Serdes, Python, TCL
AI focus
Designs hardware for AI chips and supports performance and feature development for machine learning workloads.
Model-written summary · the original posting is authoritative