Cerebras
Senior ASIC RTL Design Engineer, AI Hardware
$200K–$290K
Sunnyvale, CA · Hybrid · Senior · Full-time · Posted Oct 7, 2026
- Experience
- 8+ years delivering complex, high-performance, high-quality RTL designs.
- Education
- Master’s degree in Computer Science, Electrical Engineering, or equivalent.
About the job
Design and integrate RTL for next-generation Cerebras Wafer Scale Engines, from functional specification and micro-architecture through synthesis, design closure, and silicon bring-up.
What you'll do
- Drive functional specification, micro-architecture, RTL development, and synthesis.
- Collaborate with physical design, verification, DFT, software, and system teams to meet PPA goals and deliver product features.
- Debug functional, timing, and power issues during silicon bring-up.
What they ask for
- Master’s degree in Computer Science, Electrical Engineering, or equivalent.
- Experience with front-end chip integration and third-party IP integration; multiple successful silicon designs.
- Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning, or related fields; experience collaborating with external vendors.
- Networking stack experience including TCP/IP, RDMA, and Ethernet; knowledge of PCIe, CPU interfaces, and SerDes technology; working knowledge of Python and TCL.
Nice to have
- FPGA development toolchain experience, including place and route, floor planning, and timing analysis.
- Experience managing an external ASIC vendor through the product development cycle.
Pay
$200,000 to $290,000 annually (base salary)
Tools
RTL, TCP/IP, RDMA, Ethernet, PCIe, Serdes, Python, TCL
AI focus
Design AI hardware for the Cerebras Wafer Scale Engine, supporting high-performance machine-learning workloads.
Model-written summary · the original posting is authoritative