CesiumAstro
Principal ASIC Design Engineer - Chip Lead
$150K–$199K
Aliso Viejo, CA · On-site · Principal · Full-time · Posted Oct 2, 2026
- Experience
- Minimum of 10 years.
- Education
- Master’s in Engineering.
- Visa sponsorship
- Applicants must be U.S. citizens, lawful permanent residents, conditional residents, asylees or refugees (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.
About the job
Leads end-to-end design and delivery of high-speed mixed-signal and DSP ASICs, from system architecture through silicon production release.
What you'll do
- Define and use front-end design flows from system simulation through RTL implementation, verification, and synthesis, coordinating with backend teams.
- Integrate high-speed analog blocks into digital logic and identify architecture and microarchitecture improvements.
- Manage programs and teams, communicate with customers, and support marketing and sales interactions.
What they ask for
- Master’s in Engineering and a minimum of 10 years of experience.
- Experience with IC/ASIC development from concept through production release of silicon.
- Experience with front-end design flows, high-speed analog integration, and ASIC verification using a random constraint coverage-driven methodology.
- Fluency with Verilog and System Verilog; experience with synthesis, formal verification, and STA flow setup.
Nice to have
- Experience with low-power design flows.
- Experience implementing DSP blocks.
Pay
USD 150,000–199,000 (per-year-salary); base salary
Tools
Verilog, System Verilog, UVM, VMM, OVM, SPECMAN
Model-written summary · the original posting is authoritative