CesiumAstro
Principal Verification Engineer
$165K–$199K
Aliso Viejo, CA · On-site · Principal · Full-time · Posted Sep 28, 2026
- Experience
- At least 10 years of relevant experience with a BS degree, or at least 8 years with a Master's degree.
- Education
- BS in Computer Science, Electrical Engineering, Computer Engineering, or a related engineering discipline; alternatively, a Master's degree for the 8-year experience path.
- Visa sponsorship
- Applicants must be U.S. citizens, lawful permanent residents, conditional residents, asylees, refugees (protected individuals under 8 U.S.C. 1324b(a)(3)), or eligible to obtain required U.S. Department of State authorizations.
About the job
Develop verification methodologies, test benches, test cases, and plans for complex high-speed digital communication SoCs, collaborating with VLSI design teams and potentially providing team or project leadership.
What you'll do
- Build system-, chip-, and block-level verification infrastructure and test cases.
- Implement pseudo-random and functional-coverage verification; develop functional test and verification plans.
- Coordinate verification strategies with the VLSI Design team.
What they ask for
- Proficiency in pseudo-random and functional-coverage verification methodologies.
- Strong working knowledge of SystemVerilog and class libraries such as UVM, OVM, or VMM.
- Experience with SVA, PSL, or OVL assertions.
- Excellent written and verbal communication skills.
Nice to have
- Formal model-checking tools such as Cadence IFV or Jasper.
- Experience with DSP and digital communications.
Pay
USD 165,000–199,000 per year (base salary)
Tools
SystemVerilog, OVM, UVM, VMM, SVA, PSL, OVL, Cadence IFV
Model-written summary · the original posting is authoritative