Drimva

CesiumAstro

Senior Manager, Digital & Mixed-Signal Hardware

$218K–$266K

Westminster, CO · On-site · Manager · Full-time · Posted Oct 7, 2026

Experience
Minimum 7 years of direct digital or mixed-signal hardware engineering experience; 1–3 years of small-team technical leadership or engineering management experience preferred but not required.
Education
Bachelor’s degree or higher in Electrical Engineering or Computer Engineering required.
Visa sponsorship
Applicant must be a U.S. citizen, lawful permanent resident, conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.

About the job

Leads digital and mixed-signal hardware engineering across teams and product lines, combining technical oversight and hands-on design support with team development and delivery accountability.

What you'll do

  • Set and mature hardware design processes and standards; review designs and mentor engineers to identify risks early.
  • Lead complex debug and support board-level designs, while ensuring designs are manufacturable, testable, reliable, and ready for production.
  • Manage staffing, performance, team development, budgets, and coordination with product, manufacturing, supply chain, and other engineering groups.

What they ask for

  • Bachelor’s degree or higher in Electrical Engineering or Computer Engineering.
  • At least 7 years of direct digital or mixed-signal hardware engineering experience.
  • Expertise in high-speed digital and mixed-signal board design, with strong understanding of signal integrity and timing.
  • Experience with DFM, DFT, and production transition; proficiency with high-speed simulation and analysis tools and schematic capture and PCB layout tools.

Nice to have

  • 1–3 years of small-team technical leadership or engineering management experience.
  • Familiarity with FPGA toolchains.

Pay

USD 218,000–266,000 (per-year-salary) — base salary

Tools

Ansys SiWave, ADS SiPro, Altium, Xilinx Vivado

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 5, 2026 (UTC)