Cisco
Advanced Packaging Layout Engineering Team Leader (Substrate & Interposer) (Hybrid)
$192K–$356K
San Jose, California, US · Hybrid · Full-time · Posted Oct 26, 2026
- Experience
- Bachelor’s degree: 12+ years; Master’s degree: 8+ years; PhD: 5+ years. Also requires 5+ years in package layout or advanced PCB/package implementation.
- Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering or a related field.
About the job
Leads the San Jose package layout team and provides hands-on technical direction for advanced ASIC packaging and CoWoS projects.
What you'll do
- Lead, mentor, and coordinate package layout engineers and allocate resources across concurrent projects.
- Execute and support package layout for advanced ASIC packaging, including CoWoS, high-speed routing, power distribution, and interposers.
- Collaborate with package, SI/PI, silicon floor-planning, manufacturing, and global layout teams to resolve issues and improve methods.
What they ask for
- Bachelor’s degree in Electrical Engineering or a related field with 12+ years of work experience, or a Master’s degree with 8+ years, or a PhD with 5+ years.
- 5+ years of experience in package layout or advanced PCB/package implementation.
- Experience with high-speed routing, power distribution networks (PDN), and package layout design principles.
- Experience with industry-standard EDA tools and hands-on experience with Cadence APD+ or equivalent package layout tools.
Nice to have
- Experience leading or mentoring layout engineers or small technical teams.
- Experience with ASIC package substrate layout, CoWoS, SI/PI collaboration, vendors, or scripting languages such as Python, Perl, or TCL.
Pay
$214,100.00 to $309,800.00 USD (salary range); $214,100.00 - $356,300.00 USD (salary range, New York City Metro Area); $192,400.00 - $317,200.00 USD (salary range, non-Metro New York state & Washington state)
Tools
Cadence APD+, CoWoS, EDA, PDN, Python, Perl, TCL
Model-written summary · the original posting is authoritative