Cisco
ASIC Design Engineer Technical Lead
$166K–$308K
San Jose, California, US · Onsite Only · Full-time · Posted Jul 28, 2026
- Experience
- 8+ years with a bachelor’s degree, 6+ years with a master’s degree, or 3 years with a PhD in the specified fields.
- Education
- Bachelor’s degree in Electrical or Computer Engineering, Master’s degree in Electrical Engineering or Computer Engineering, or PhD in Electrical Engineering or Computer Engineering.
About the job
Leads ASIC design work from architecture and specification through RTL implementation, tape-out, validation, and debugging.
What you'll do
- Contribute to chip architecture and micro-architecture specifications, and implement Verilog RTL to meet timing and performance requirements.
- Collaborate with verification and physical design teams to resolve bugs, close code coverage, and address timing and place-and-route issues.
- Debug simulation, software bring-up, and customer failures; perform post-silicon validation and mentor junior engineers.
What they ask for
- Bachelor’s degree in Electrical or Computer Engineering and 8+ years of ASIC Design experience; or a Master’s degree in Electrical Engineering or Computer Engineering and 6+ years; or a PhD in Electrical Engineering or Computer Engineering and 3 years.
- Verilog/System Verilog programming experience.
- Interactive and waveform debug experience.
- Experience delivering ASIC designs from specification to tape-out, and in architecture and micro-architecture development.
Nice to have
- Experience resolving setup and hold timing violations with RTL modification.
- Scripting experience (Python, Perl, TCL, shell programming).
Pay
$186,900.00 to $267,700.00 USD base salary; $186,900.00 - $307,800.00 USD base salary; $166,300.00 - $274,100.00 USD base salary
Tools
Verilog, System Verilog, Python, Perl, TCL
Model-written summary · the original posting is authoritative