Cisco
ASIC Design Verification Engineer
$149K–$282K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 12, 2026
- Experience
- 7+ years with a bachelor’s degree, 4+ years with a master’s degree, or 1+ year with a PhD.
- Education
- Bachelor’s, master’s, or PhD in electrical engineering, computer science, computer engineering, or a related field.
About the job
Verifies ASIC designs for Cisco high-end switching products, from individual blocks through top-level systems.
What you'll do
- Perform end-to-end verification of design blocks and top-level designs, including multi-chip and system simulation.
- Develop simulation models, test plans, tests, coverage, and performance analyses; build testbench components such as scoreboards, agents, sequencers, and monitors.
- Collaborate with hardware and software designers and vendors.
What they ask for
- Bachelor’s degree in electrical engineering, computer science, computer engineering, or a related field and 7+ years of related experience; or a master’s degree and 4+ years; or a PhD and 1+ year.
- Experience with System Verilog/UVM.
- Experience with ASIC design and verification processes, debugging, methodology, and tools.
- Experience verifying ASIC blocks, clusters, or full-chip designs.
Nice to have
- Post-silicon lab bring-up experience; experience with Linux, C/C++, Python, or Perl.
- Experience in networking or formal verification.
Pay
$167,700.00 to $245,200.00 USD (salary range; base salary excludes incentive compensation, equity, and benefits); $167,700.00 - $282,000.00 USD (salary range; base salary); $149,100.00 - $250,900.00 USD (salary range; base salary)
Tools
System Verilog, UVM, Linux, C/C++, Python, Perl
Model-written summary · the original posting is authoritative