Cisco
ASIC Design Verification Engineer
$138K–$256K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 16, 2026
- Experience
- 5 years of ASIC experience with a bachelor’s degree, or 3 years with a master’s degree, or 0 years of related experience with a PhD.
- Education
- Bachelor’s degree, master’s degree, or PhD.
About the job
Develops and maintains ASIC design-verification environments, tests, and coverage to qualify complex chips and support integration and bring-up.
What you'll do
- Build and maintain block, cluster, and top-level DV infrastructure; create block- and cluster-level environments from scratch.
- Develop and run directed and constraint-random tests, review code and functional coverage, and run Gate Level Simulations on netlists.
- Collaborate on debugging during integration and post-silicon bring-up, and support design testing in emulation environments.
What they ask for
- System Verilog and UVM methodology experience.
- Hands-on experience building reusable, scalable test benches from scratch.
- Scripting experience with Perl and/or Python.
Nice to have
- Experience with forwarding logic, parsers, or P4; emulation platforms such as Veloce, Palladium, Zebu, or HAPS; or formal verification tools such as IEV or VC Formal.
- Domain knowledge in one or more of PCIe, CXL, Ethernet, RDMA, DDR, or TCP.
Pay
$155,000.00 to $222,600.00 USD base salary; $155,000.00 - $256,000.00 USD base salary; $138,100.00 - $227,900.00 USD base salary
Tools
System Verilog, UVM, Perl, Python, Veloce, Palladium, Zebu, HAPS
Model-written summary · the original posting is authoritative