Cisco
ASIC Design Verification Engineer
$149K–$282K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 16, 2026
- Experience
- Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience.
- Education
- Bachelor’s, Master’s, or PhD; no equivalent-experience alternative stated.
About the job
Leads ASIC verification strategy, teams, and reusable infrastructure across programs, and supports complex issue resolution through bring-up and post-silicon validation.
What you'll do
- Set verification vision and strategy and lead architecture of scalable, reusable verification infrastructure.
- Mentor verification teams and drive cross-functional improvements in verification efficiency, quality, and coverage.
- Influence ASIC design and lead root-cause analysis during bring-up and post-silicon validation.
What they ask for
- Experience in System Verilog, UVM, and verification methodologies.
- Experience architecting verification strategies for complex ASIC programs.
- Experience leading verification teams or projects.
- Experience with scripting (Python, Perl) and C/C++ programming language.
Nice to have
- Experience in data center, Hyperscalers, or AI Networking technologies.
- Experience with advanced emulation, prototyping, and formal verification tools at scale.
Pay
$167,700.00 to $245,200.00 USD base salary; $167,700.00 - $282,000.00 USD base salary (New York City Metro Area); $149,100.00 - $250,900.00 USD base salary (Non-Metro New York state & Washington state)
Tools
System Verilog, UVM, Python, Perl, C/C++
AI focus
Verification leadership for ASIC platforms described as powering the AI era; no specific AI development work is stated.
Model-written summary · the original posting is authoritative