Cisco
ASIC Design Verification Engineer
$138K–$256K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 14, 2026
- Experience
- 5 years of relevant technical experience with a bachelor’s degree, or 3 years with a related master’s degree.
- Education
- Bachelor’s degree in Computer, Electrical, or Electronics Engineering, or a master’s degree in a related field.
About the job
Develops and runs verification infrastructure, tests, and coverage for ASIC designs, collaborating with hardware and software teams through integration and bring-up.
What you'll do
- Build and maintain block, cluster, and top-level design verification environments; create block and cluster environments from scratch.
- Develop test plans and constraint-random and directed tests; implement and review code and functional coverage.
- Run gate-level simulations, support emulation, and debug integration and post-silicon issues with cross-functional teams.
What they ask for
- Bachelor’s degree in Computer, Electrical, or Electronics Engineering plus 5 years of relevant technical experience, or a related master’s degree plus 3 years of relevant technical experience, focused on ASIC design and verification.
- Experience with System Verilog or UVM methodology.
- Experience building reusable, scalable test benches from scratch.
- Experience scripting with Perl and/or Python.
Nice to have
- Experience with forwarding logic, parsers, or P4; emulation platforms such as Veloce, Palladium, Zebu, or HAPS; or formal verification tools such as IEV or VC Formal.
- Domain knowledge of one or more protocols: PCIe, CXL, Ethernet, RDMA, DDR, or TCP.
Pay
$155,000.00 to $222,600.00 USD base salary; $155,000.00 - $256,000.00 USD base salary; $138,100.00 - $227,900.00 USD base salary
Tools
System Verilog, UVM, Perl, Python, Veloce, Palladium, Zebu, HAPS
AI focus
The role verifies ASIC hardware platforms supporting data center solutions in the AI era; no direct AI development work is specified.
Model-written summary · the original posting is authoritative