Cisco
ASIC Design Verification Engineer I (Full Time) - United States
$95K–$157K
San Jose, California, US +2 · Onsite Only · Full-time · Posted Oct 26, 2026
- Location
- San Jose, California, US
RTP, North Carolina, US
Carlsbad, California, US - Education
- Bachelor's degree; qualifying education and work experience should be in ASIC Design, Design Verification, or a related field. Degree must have been completed within the past 3 years or be expected within the next 12 months.
About the job
Verifies ASIC designs for Cisco hardware platforms using simulation, emulation, and ASIC bring-up, developing test environments and driving verification to closure.
What you'll do
- Maintain and enhance existing design verification environments and build test benches for new blocks.
- Write test plans and test cases, debug regression failures, and drive module verification closure.
- Implement and review code and functional coverage to ensure complete verification coverage.
What they ask for
- Bachelor's degree completed within the past 3 years or expected within the next 12 months, in ASIC Design, Design Verification, or a related field.
- Experience with System Verilog and UVM methodology.
- Experience scripting using Perl and/or Python.
Nice to have
- Experience with functional coverage, constrained random DV environments, and verifying complex ASIC blocks, clusters, or SoC top levels.
- Experience with Veloce/HAPS and building test benches from scratch.
Pay
$107,800.00 - $157,400.00 USD base salary; $94,800.00 - $140,000.00 USD base salary
Tools
System Verilog, UVM, Perl, Python, Veloce/HAPS
Model-written summary · the original posting is authoritative