Cisco
ASIC Design Verification Engineer II Full Time - United States
$112K–$203K
San Jose, California, US +1 · Hybrid · Full-time · Posted Oct 26, 2026
- Location
- San Jose, California, US
RTP, North Carolina, US - Experience
- Master’s degree with 0 years of work experience, or Bachelor’s degree with 2 years of work experience. Qualifying education and experience must have been completed within the past 3 years or be expected within the next 12 months.
- Education
- Master’s degree or Bachelor’s degree in ASIC Engineering, Verification, or a related field.
About the job
Verifies ASICs in simulation, emulation, and bring-up by developing verification environments, test benches, test cases, and coverage to support Cisco hardware platforms.
What you'll do
- Maintain and enhance existing design verification environments; build test benches for new blocks.
- Write test plans and test cases, debug regression failures, and drive module verification to closure.
- Implement and review code and functional coverage to ensure complete verification.
What they ask for
- A qualifying Master’s degree with 0 years of work experience, or Bachelor’s degree with 2 years of work experience; education and experience must be in ASIC Engineering, Verification, or a related field.
- Experience with System Verilog and UVM methodology.
- Experience scripting with Perl and/or Python.
Nice to have
- Experience with functional coverage, constrained-random verification, and verification of complex ASIC blocks, clusters, or SoC top levels.
- Experience with Veloce/HAPS and building test benches from scratch, including SystemVerilog constraints, structures, and classes.
Pay
$125,700.00 - $203,100.00 USD base salary; $111,700.00 - $180,800.00 USD base salary
Tools
System Verilog, UVM, Perl, Python, Veloce, HAPS
Model-written summary · the original posting is authoritative