Cisco
ASIC Design Verification Engineer, Technical Leader
$166K–$308K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 1, 2026
- Experience
- Bachelor's with 8+ years or Master's degree with 6+ years of relevant experience.
- Education
- Bachelor's or Master's degree.
About the job
Verifies Cisco ASICs in simulation, emulation, and bring-up by building and maintaining design-verification environments and driving blocks to verification closure.
What you'll do
- Maintain and enhance existing DV environments; build test benches for new blocks.
- Write test plans and cases, debug regressions, and drive module verification closure.
- Implement and review code and functional coverage; use AI tools to improve DV quality and processes.
What they ask for
- Prior experience with System Verilog and UVM methodology.
- Experience verifying complex ASIC/SoC blocks, clusters, and/or top level, and building test benches from scratch.
- Hands-on experience with System Verilog constraints, structures, and classes; functional coverage and constrained-random DV environments.
- Perl and/or Python scripting skills.
Nice to have
- Domain experience with one or more of PCIe, CXL, Ethernet, AHB/AXI, DDR, or MMU; Veloce/HAPS experience.
- Formal verification (iev/vc formal) knowledge.
Pay
$186,900.00 to $267,700.00 USD base salary; $186,900.00 - $307,800.00 USD base salary (New York City Metro Area); $166,300.00 - $274,100.00 USD base salary (Non-Metro New York state & Washington state)
Tools
System Verilog, UVM, Perl, Python, PCIe, CXL, Veloce/HAPS, iev/vc formal
AI focus
Use AI tools to develop innovative methods and processes to improve design-verification quality.
Model-written summary · the original posting is authoritative