Cisco
ASIC Design Verification Technical Leader
$166K–$308K
Carlsbad, California, US +1 · Onsite Only · Full-time · Posted Sep 30, 2026
- Location
- Carlsbad, California, US
Allentown, Pennsylvania, US - Experience
- 8+ years with a bachelor’s degree; 6+ years of ASIC Design experience with a master’s degree; or 3+ years in ASIC Design Verification with a PhD.
- Education
- Bachelor’s in Electrical or Computer Engineering; or Master’s or PhD in Electrical Engineering or Computer Engineering.
About the job
Leads ASIC design verification for silicon photonics driver integrated circuits, from verification strategy and block/chip-level execution through silicon bring-up and debugging.
What you'll do
- Define verification methodology and standards across projects and sites; lead block- and chip-level verification.
- Review specifications and design architecture for testability; mentor verification engineers.
- Debug silicon and system-level issues and support post-silicon bring-up and performance optimization.
What they ask for
- Bachelor’s degree in Electrical or Computer Engineering and 8+ years of ASIC Design Verification experience; or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience; or PhD in Electrical Engineering or Computer Engineering and 3+ years in ASIC Design Verification.
- Experience in System Verilog, UVM, and verification methodologies.
- Experience owning and delivering verification for large-scale SoCs or subsystems, and leading verification teams or projects.
- Experience with scripting and automation such as Python, Perl, TCL, or Shell Scripts.
Nice to have
- Expertise verifying SerDes IP, D2D PHY IP, ODSP, integrated transceiver features, CPU subsystems, and protocols.
- Experience with Formal Verification, emulation and prototyping platforms (Veloce, HAPS), and collaboration with architecture and design teams on verification strategy.
Pay
$166,300.00 to $238,300.00 USD (base salary); $186,900.00 - $307,800.00 USD (base salary, New York City Metro Area); $166,300.00 - $274,100.00 USD (base salary, Non-Metro New York state & Washington state)
Tools
System Verilog, UVM, Python, Perl, TCL, Shell Scripts, Verilog, Veloce
Model-written summary · the original posting is authoritative