Cisco
ASIC DFT DV Technical Leader (Hybrid)
$166K–$308K
San Jose, California, US · Hybrid · Full-time · Posted Oct 13, 2026
- Experience
- Bachelor’s + 8 years, or Master’s + 6 years, or PhD + 3 years of related experience.
- Education
- Bachelor’s, Master’s, or PhD.
About the job
Leads DFT verification for Silicon One ASICs, planning tests and developing testbenches to validate DFT architecture across implementation and post-silicon flows.
What you'll do
- Plan tests and develop testbenches for DFT architecture supporting ATE screening, in-system test, debug, and diagnostics.
- Collaborate with RTL, design-verification, and physical-design teams to integrate and validate test logic through implementation and post-silicon validation.
- Drive reusable test and debug methodologies and standards for new silicon device models, including bare-die and stacked-die designs.
What they ask for
- Prior experience in test planning based on complex design specifications.
- Prior experience developing testbenches using System Verilog.
- Experience debugging using DVE/Verdi.
- Experience with TCL, Python, or Perl.
Nice to have
- UVM and advanced System Verilog knowledge.
- Knowledge of JTAG protocol, scan architecture, MBIST, and boundary scan.
Pay
$186,900.00 to $267,700.00 USD base salary; $186,900.00 - $307,800.00 USD base salary; $166,300.00 - $274,100.00 USD base salary
Tools
System Verilog, DVE, Verdi, TCL, Python, Perl, UVM, JTAG
Model-written summary · the original posting is authoritative