Cisco
ASIC DFT Emulation Technical Lead
$166K–$308K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 5, 2026
- Experience
- Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
- Education
- Bachelor’s, Master’s, or PhD; no equivalent experience alternative stated.
About the job
Leads DFT emulation strategy and execution for Cisco Silicon One ASICs, validating test architectures and supporting silicon bring-up.
What you'll do
- Architect emulation environments and lead pre-silicon test plan execution.
- Validate scan, MBIST, and JTAG architectures on emulation platforms; troubleshoot issues with cross-functional teams.
- Support post-silicon pattern conversion and test coverage.
What they ask for
- Prior emulation experience on Palladium, Veloce, or Zebu, including compilation and debug.
- Prior experience with Verilog and System Verilog.
- Prior experience with C/C++ and scripting with Tcl or Python/Perl.
Nice to have
- Experience defining DFT emulation strategy; familiarity with JTAG, scan architecture, MBIST, and boundary scan.
- UVM and advanced System Verilog knowledge; post-silicon validation or debugging experience.
Pay
$186,900.00 to $267,700.00 USD base salary; $186,900.00 - $307,800.00 USD base salary; $166,300.00 - $274,100.00 USD base salary
Tools
Palladium, Veloce, Zebu, Verilog, System Verilog, C/C++, Tcl, Python/Perl
Model-written summary · the original posting is authoritative