Cisco
ASIC DFT Engineer
$139K–$282K
Austin, Texas, US +1 · Hybrid · Full-time · Posted Oct 28, 2026
- Location
- Austin, Texas, US
San Jose, California, US - Experience
- At least 7 years.
- Education
- Bachelor's or Master's Degree in Electrical or Computer Engineering required.
About the job
Drives design-for-test requirements and quality processes for networking chips from early design through implementation and post-silicon validation.
What you'll do
- Coordinate with front-end RTL and backend physical design teams to understand chip architecture and establish DFT requirements early in design.
- Drive DFT and quality processes across implementation and post-silicon validation.
- Support physical design signoff activities.
What they ask for
- Bachelor's or Master's degree in Electrical or Computer Engineering.
- Experience with JTAG protocols, scan and BIST architectures, including memory BIST and boundary scan.
- Experience with ATPG and EDA tools, including TestMax, Tetramax, Tessent tool sets, and PrimeTime.
- Experience with gate-level simulation and VCS or other simulators; post-silicon validation and debug, ATE patterns, and P1687.
Nice to have
- Verilog design for custom DFT logic and IP integration; familiarity with functional verification.
- DFT CAD development, test static timing analysis, or post-silicon validation using DFT patterns.
Pay
$139,300.00 to $203,600.00 USD base salary; $167,700.00 - $282,000.00 USD base salary; $149,100.00 - $250,900.00 USD base salary
Tools
JTAG, Scan, BIST, ATPG, TestMax, Tetramax, Tessent, PrimeTime
Model-written summary · the original posting is authoritative