Cisco
ASIC DFT Engineer - Acacia (Hybrid)
$138K–$256K
San Jose, California, US · Hybrid · Full-time · Posted Oct 27, 2026
- Experience
- Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
- Education
- Bachelors, Master, or PhD; or equivalent related work experience.
About the job
Supports DFT implementation, validation, and signoff for ASIC/SoC designs, helping deliver test coverage and manufacturability.
What you'll do
- Implement and validate scan, scan compression, OCC, MBIST, boundary scan, and related DFT logic; support block- and chip-level integration.
- Run DFT checks, generate and validate ATPG patterns, analyze coverage, and debug violations, chain failures, and simulation issues.
- Automate DFT flows and reporting with scripts; document results and support silicon diagnosis and yield learning.
What they ask for
- Experience with ASIC DFT implementation or validation.
- Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent.
- Experience with scan architecture, scan compression, ATPG, MBIST, OCC, test-mode controls, and stuck-at and transition fault models.
- Experience debugging DFT violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures; scripting experience using Tcl, Python, Perl, or shell.
Nice to have
- Experience with hierarchical DFT methodology and block-level signoff.
- Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows.
Pay
$155,000.00 to $222,600.00 USD base salary; $155,000.00 - $256,000.00 USD base salary; $138,100.00 - $227,900.00 USD base salary
Tools
Siemens Tessent, Synopsys DFT Compiler/TestMAX, Tcl, Python, Perl, shell, IJTAG / IEEE 1687, IEEE 1500
Model-written summary · the original posting is authoritative