Cisco
ASIC DFT Engineering Technical Leader
$166K–$308K
San Jose, California, US +2 · Hybrid · Full-time · Posted Oct 22, 2026
- Location
- San Jose, California, US
Austin, Texas, US
Seattle, Washington, US - Experience
- 8+ years with a bachelor's degree; 6+ years with a master's degree; or 3+ years with a PhD.
- Education
- Bachelor’s, master’s, or PhD in Electrical or Computer Engineering.
About the job
Leads design-for-test (DFT) and quality activities for ASIC implementation, from early chip design through post-silicon validation, collaborating with RTL, physical design, and ATE teams.
What you'll do
- Drive DFT requirements early in the design cycle with RTL and backend physical design teams.
- Lead DFT and quality processes through implementation and post-silicon validation, with exposure to physical design signoff.
- Work with ATE engineers on test-pattern translation and validation.
What they ask for
- Experience with ATPG and EDA tools such as TestMax, Tetramax, or Tessent.
- Gate-level simulation experience, including timing-based simulations with SDF and debugging with VCS or other simulators.
- Post-silicon validation and debug experience.
- Scan insertion experience.
Nice to have
- Verilog design, custom DFT logic, IP integration, and functional verification familiarity; JTAG protocols (p1500, p1687) or SSN experience.
- Tcl, Python, or Perl scripting; test static timing analysis constraints development and timing closure.
Pay
$186,900.00 to $267,700.00 USD base salary; $186,900.00 - $307,800.00 USD base salary (New York City Metro Area); $166,300.00 - $274,100.00 USD base salary (non-metro New York state & Washington state)
Tools
ATPG, TestMax, Tetramax, Tessent, SDF, VCS, Verilog, Tcl
Model-written summary · the original posting is authoritative