Cisco
ASIC DFT STA Engineer
$149K–$282K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 22, 2026
- Experience
- Bachelor’s + 7 years, Master’s + 4 years, or PhD + 1 year of related experience. Preferred: Master’s degree + 10 years of relevant experience.
- Education
- Bachelor’s, Master’s, or PhD, with the stated related-experience alternatives.
About the job
Develop and verify timing constraints for ASIC DFT, help drive DFT quality through implementation and post-silicon validation, and support physical-design signoff.
What you'll do
- Develop and verify timing constraints, collaborating with cross-functional teams and communicating timing data.
- Drive DFT and quality processes through implementation and post-silicon validation.
- Support physical design signoff activities.
What they ask for
- Prior experience with RTL design, CDC/RDC and conformal verification, and SDC development.
- Prior experience in timing-constraint development and verification.
- Programming experience with at least two of Perl, TCL, Python, or Makefile.
- Bachelor’s + 7 years, Master’s + 4 years, or PhD + 1 year of related experience.
Nice to have
- Master’s degree + 10 years of relevant experience.
- Experience with PCIE or TSMC memory timing constraints; DFT timing closure; Synopsys TCM/Primetime; Synopsys Fusion/Design Compiler; or Tessent DFT insertion.
Pay
$167,700.00 to $245,200.00 (base salary); $167,700.00 - $282,000.00 (base salary, New York City Metro Area); $149,100.00 - $250,900.00 (base salary, non-metro New York state & Washington state)
Tools
RTL, CDC/RDC, conformal verification, SDC, Perl, TCL, Python, Makefile
AI focus
The role develops networking chips for platforms described as powering the AI era; no specific AI development work is stated.
Model-written summary · the original posting is authoritative