Cisco
ASIC DFT Technical Leader
$166K–$308K
San Jose, California, US +1 · Hybrid · Full-time · Posted Oct 19, 2026
- Location
- San Jose, California, US
Austin, Texas, US - Experience
- At least 10 years.
- Education
- Bachelor's or Master's degree in Electrical or Computer Engineering.
About the job
Leads DFT requirements and quality processes for ASIC design and implementation, collaborating across RTL, physical design, and post-silicon validation teams.
What you'll do
- Drive DFT requirements early in the chip design cycle with front-end RTL and backend physical design teams.
- Lead DFT and quality processes throughout implementation and post-silicon validation.
- Contribute to next-generation networking chip development and support physical design signoff activities.
What they ask for
- Bachelor's or Master's degree in Electrical or Computer Engineering.
- Experience with JTAG protocols, scan and BIST architectures, ATPG, and DFT EDA tools.
- Experience with gate-level simulation and debugging using VCS or other simulators.
- Post-silicon validation and debug experience, including ATE patterns and P1687.
Nice to have
- Verilog design for custom DFT logic and IP integration, with familiarity in functional verification.
- DFT CAD development, test static timing analysis, or post-silicon validation using DFT patterns.
Pay
$186,900.00 to $267,700.00 (base salary); $186,900.00 - $307,800.00 (base salary, New York City Metro Area); $166,300.00 - $274,100.00 (base salary, non-Metro New York state & Washington state)
Tools
Jtag, Scan, BIST, ATPG, TestMax, Tetramax, Tessent, PrimeTime
Model-written summary · the original posting is authoritative