Cisco
ASIC DFT Technical Leader
$166K–$308K
San Jose, California, US +1 · Hybrid · Full-time · Posted Oct 19, 2026
- Location
- San Jose, California, US
Austin, Texas, US - Experience
- 10+ years of industry experience in ASIC digital design.
About the job
Leads ASIC design work focused on structural and functional testing, diagnostic features, IP development and integration, and test access for Cisco Silicon One chips.
What you'll do
- Collaborate with front-end RTL and backend physical design teams to understand chip architecture.
- Drive structural and functional test, diagnostic feature implementation, and IP development and integration.
- Develop test access, including high-speed I/O with protocol.
What they ask for
- 10+ years of industry experience in ASIC digital design.
- Experience coding in Verilog/System Verilog.
- Experience with front-end tools, including Verilog simulators, linting, CDC checkers, synthesis, and formal verification.
- Experience with industry-standard interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories.
Nice to have
- Experience with power optimization, power intent (UPF), and power estimation.
- Experience with DFT/MBIST or post-silicon debug.
Pay
$186,900.00 to $267,700.00 USD (base salary); $186,900.00 - $307,800.00 USD (base salary); $166,300.00 - $274,100.00 USD (base salary)
Tools
Verilog, System Verilog, AMBA, AXI, APB, AHB, JTAG, UPF
Model-written summary · the original posting is authoritative