Cisco
ASIC DFT Technical Leader- MBIST
$192K–$356K
San Jose, California, US +1 · Hybrid · Full-time · Posted Sep 3, 2026
- Location
- San Jose, California, US
Austin, Texas, US - Experience
- 12+ years with a Bachelor’s, or 10+ years with a Master’s, in ASIC DFT.
- Education
- Bachelor’s in Electrical Engineering, or Master’s.
About the job
Leads MBIST methodology and develops reusable memory-test architecture for Cisco Silicon One networking chips.
What you'll do
- Lead MBIST methodology for Silicon One chips and design and implement robust, reusable MBIST architecture.
- Specify comprehensive MBIST architecture independent of technology and tools.
- Define MBIST requirements for advanced technology nodes and advanced technology packages.
What they ask for
- Bachelor’s in Electrical Engineering with 12+ years of ASIC DFT experience, or Master’s with 10+ years.
- Experience with memory architectures (such as SRAM and DRAM) and failure modes.
- Experience with industry-standard DFT tools, such as Synopsys DesignWare, SMS, TestMax, or Mentor Graphics Tessent.
- Scripting skills in Python, TCL, or Perl for test-generation and analysis automation.
Nice to have
- Experience in Verilog/System Verilog.
- Experience addressing memory failure correlation in production.
Pay
$214,100.00 to $309,800.00 (base salary); $214,100.00 - $356,300.00 (base salary, New York City Metro Area); $192,400.00 - $317,200.00 (base salary, non-Metro New York state & Washington state)
Tools
SRAM, DRAM, Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent, Python, TCL
Model-written summary · the original posting is authoritative