Cisco
ASIC Engineer
$149K–$282K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 28, 2026
- Experience
- 7+ years of ASIC design experience with a bachelor's degree, or 4+ years with a master's degree.
- Education
- Bachelor's or master's degree in Electrical or Computer Engineering.
About the job
Designs and delivers high-performance ASIC subsystems, from architecture and RTL through tape-out, while coordinating with verification and physical design teams.
What you'll do
- Own ASIC subsystem front-end design and implementation, including high-performance Verilog/SystemVerilog RTL that meets power, performance, and area targets.
- Lead specifications and technical reviews, and coordinate execution across architecture, design, verification, and physical implementation teams.
- Debug issues through simulation, system bring-up, and post-silicon validation; mentor engineers and improve reusable design practices.
What they ask for
- ASIC design experience delivering silicon from microarchitecture and specification through RTL coding and tape-out, including multiple tape-outs at advanced technology nodes.
- High-performance RTL design using Verilog/SystemVerilog.
- Understanding of timing closure, power optimization, and clock gating.
- Experience with ASIC development flows including simulation, synthesis, and static timing analysis.
Nice to have
- Documentation, problem-solving, and technical communication skills.
- Cross-functional collaboration experience.
Pay
$167,700.00 to $245,200.00 USD base salary; $167,700.00 - $282,000.00 USD base salary; $149,100.00 - $250,900.00 USD base salary
Tools
Verilog, SystemVerilog
Model-written summary · the original posting is authoritative