Cisco
ASIC Engineering Technical Leader
$166K–$308K
San Jose, California, US +1 · Hybrid · Full-time · Posted Oct 23, 2026
- Location
- San Jose, California, US
Carlsbad, California, US - Experience
- Bachelors + 8 years, or Masters + 6 years, or PhD + 3 years of related experience.
- Education
- Bachelor’s, Master’s, or PhD; no equivalent-experience alternative stated.
About the job
Leads physical design implementation and flow development for high-speed optical transceiver and driver ICs, from RTL through GDSII signoff and tapeout.
What you'll do
- Lead physical design, floorplanning, placement, timing closure, signoff, and tapeout across advanced technology nodes.
- Develop and scale implementation flows using automation to improve quality of results and turnaround time.
- Coordinate physical design execution with RTL, Analog, DFT, Packaging, and CAD teams.
What they ask for
- Experience in ASIC/SoC physical design and implementation in advanced technology nodes.
- Hands-on experience with the full physical design flow at block and/or chip level.
- Hands-on expertise in EDA flows, back-end signoff criteria, and workflow automation using Python, TCL, and Shell scripts.
Nice to have
- Experience closing high-speed, high-density, macro-dominant, or I/O cell-intensive designs.
- Expertise in STA methodology, SDC constraints, timing analysis, and timing ECO generation.
Pay
$186,900.00 to $267,700.00 (base salary); $186,900.00 - $307,800.00 (base salary, New York City Metro Area); $166,300.00 - $274,100.00 (base salary, non-Metro New York state & Washington state)
Tools
Python, TCL, Shell, EDA, STA, SDC, RTL, GDSII
AI focus
Physically realizes optical transceivers and driver ICs that power AI/ML data centers.
Model-written summary · the original posting is authoritative