Cisco
ASIC Link Modeling Technical Leader
$192K–$356K
Carlsbad, California, US +1 · Onsite Only · Full-time · Posted Oct 6, 2026
- Location
- Carlsbad, California, US
Allentown, Pennsylvania, US - Experience
- Bachelor’s + 12 years of related experience, or Master’s + 8 years of related experience, or PhD + 5 years of ASIC link modeling experience. Preferred experience: 8–12 years.
- Education
- Bachelor’s, Master’s, or PhD.
About the job
Develops and validates behavioral models and link simulations for Cisco silicon photonics systems, including high-speed SerDes, optical DSP, and die-to-die interfaces.
What you'll do
- Build link models and run simulations to assess jitter, noise, crosstalk, and bit error rate.
- Define and optimize transceiver architectures, equalization, clock and data recovery, and DSP algorithms through modeling.
- Debug simulations, correlate pre-silicon models with lab measurements, and collaborate on IBIS-AMI models and product release.
What they ask for
- Proficiency in Python, C/C++, and MATLAB.
- Understanding of high-speed communication theory, transmission line theory, SerDes, Ethernet, D2D PHY protocols, and DSP fundamentals.
- Experience with EDA and SI simulation tools and link modeling methodologies.
- Analytical, debugging, communication, and teamwork skills.
Nice to have
- Experience with optical DSP, integrated transceiver features, and PAM4 modulation.
- IBIS-AMI development, Linux and scripting automation, ASIC/SoC design flow, or post-silicon validation experience.
Pay
$192,400.00 to $275,800.00 USD (base salary); $214,100.00 - $356,300.00 USD (base salary); $192,400.00 - $317,200.00 USD (base salary)
Tools
Python, C/C++, MATLAB, Keysight ADS, Synopsys HSPICE, Cadence, Perl, TCL
Model-written summary · the original posting is authoritative