Cisco
ASIC Physical Design Engineer
$138K–$256K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 27, 2026
- Experience
- 5+ years with a Bachelor’s Degree, 3+ years with a Master’s Degree, or 0+ years with a PhD.
- Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering.
About the job
Implements and optimizes RTL-to-GDSII physical design flows for advanced-node networking chips, focusing on timing, performance, die size, and sign-off.
What you'll do
- Drive implementation including floorplanning, place and route, static timing analysis, power integrity, equivalence checks, and timing ECOs.
- Improve backend tools, flows, methodologies, and STA automation; guide clock tree synthesis and timing convergence.
- Collaborate with RTL, DFT, implementation, EDA vendors, and tool/flow teams.
What they ask for
- Bachelor’s Degree in Electrical Engineering with 5+ years of Physical Design experience, Master’s Degree in Electrical Engineering with 3+ years, or PhD in Electrical Engineering with 0+ years.
- Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
- Experience with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre.
Nice to have
- Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
- Experience with static timing analysis and concepts, timing constraints and exceptions, corners/voltage definitions, or Python, TCL, or Perl programming.
Pay
$155,000.00 to $222,600.00 USD base salary; $155,000.00 - $256,000.00 USD base salary; $138,100.00 - $227,900.00 USD base salary
Tools
Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre, Tweaker, Python, TCL, Perl
Model-written summary · the original posting is authoritative