Cisco
ASIC Physical Design Engineer II (Full Time) - United States
$112K–$203K
San Jose, California, US · Hybrid · Full-time · Posted Oct 1, 2026
- Experience
- Master's degree with 0 years of work experience, or Bachelor's degree with 2 years of work experience; qualifying education and experience must have been completed within the past 3 years or be expected within the next 12 months.
- Education
- Master's or Bachelor's degree; no equivalent experience alternative stated.
- Visa sponsorship
About the job
Implements and optimizes RTL-to-GDSII physical design for advanced-node networking chips, focusing on floor planning, timing closure, backend flows, and cross-team delivery.
What you'll do
- Own RTL-to-GDSII implementation, including floor planning, place and route, clock and power distribution, and timing convergence.
- Perform multi-mode/multi-corner static timing analysis, reviews, sign-offs, and timing ECOs; develop STA automation scripts.
- Analyze design and flow gaps, improve tools and methodologies, and collaborate with RTL, DFT, EDA vendors, and tool owners.
What they ask for
- Meet one education/work-experience pathway: a Master's degree with 0 years of work experience, or a Bachelor's degree with 2 years of work experience; qualifying education and experience must be in ASIC Physical Design, ASIC design, engineering, or a related field.
- Foundational knowledge of ASIC physical design and implementation flows, gained through academic projects, internships, or relevant coursework.
- Understand physical design concepts including floor planning, clock tree synthesis, power distribution, and I/O planning.
- Exposure to the physical design lifecycle, including logic synthesis, placement, routing, and basic timing closure.
Nice to have
- Proficiency in Python, Tcl, or Perl for automation and data analysis.
- Hands-on exposure to industry-standard EDA tools, physical verification processes, or static timing analysis tools.
Pay
$125,700.00 - $203,100.00 USD base salary (New York City Metro Area); $111,700.00 - $180,800.00 USD base salary (Non-Metro New York state & Washington state)
Tools
Python, Tcl, Perl, Cadence Innovus, Synopsys ICC2, Synopsys Design Compiler, Mentor Calibre, PrimeTime
AI focus
No AI-specific work is stated; the role supports networking chips described as powering the AI era.
Model-written summary · the original posting is authoritative